1) Field of the Invention
The present invention relates to a controller that controls an access to a synchronous semiconductor memory device.
2) Description of the Related Art
The operating speed of the microprocessors has been constantly improving. Dynamic random-access memories (DRAMs) that operate synchronously with the clock signal (i.e., SDRAMs), which can be accessed speedily, have appeared in the market. The internal operation of the SDRAM is divided into row series operation and column series operation.
The SDRAM has a bank structure in which a memory cell array is divided into independent banks. This structure makes the operating speed of the SDRAM faster.
FIG. 12 shows a large scale integration (LSI) 3 that includes a conventional SDRAM control module 90. The SDRAM control module 90 includes an SDRAM access control section 1. The SDRAM access control section 1 generates an SDRAM control signal 23. The SDRAM control signal 23 may be a row address strobe signal RAS, column address strobe signal CAS, WE signal, or CS signal. The SDRAM access control section 1 also generates an address signal 24 that contains a bank address. The SDRAM access control section 1 generates the SDRAM control signal 23 based on the input of a signal 21. The signal 21 (access request signal) requests access to the SDRAM 300. The SDRAM access control section 1 generates the address signal based on the input of an address signal 22. The SDRAM control signal 23 and the address signal 24 are input into the SDRAM 300 at a predetermined timing to write and read a data signal 25 onto and from the SDRAM 300.
The operation for reading data from the SDRAM is explained next. The signal 21 and the address signal 22 are input into the SDRAM control module 90 from a module that is not shown in the figure. The SDRAM access control section 1 issues a row activation command AC, a read command RD, and a bank deactivation command PR to the SDRAM 300 after receiving the signal 21 and the address signal 22. The bank deactivation command PR is a precharge command. These commands are generated based on a combination of high logical level (H) and low logical level (L) of the SDRAM control signals 23 that could be the RAS, CAS, WE, CS signals. The address signal 22 is processed into a format suited for the SDRAM 300 by multiplexing process. The address signal 22 is transmitted to the SDRAM 300 by the SDRAM access control section 1 in the form of the address signal 24. A row address and then a column address is transmitted to the SDRAM 300. The SDRAM 300 outputs the data signal 25 to a data bus after passing through the CAS latency on execution of the read command RD. The data signal 25 output from the SDRAM 300 is read by a module, which is not shown in the diagram, in LSI 3.
FIG. 13 is a time chart that explains the operation in detail. It has been assumed here that the same row in the same bank of the SDRAM 300 is accessed twice. The burst output length when transferring the burst of the SDRAM 300 is 1 and is programmed before accessing the SDRAM 300.
The signal 21 is asserted in clock cycle 1. As a result, the SDRAM access control section 1 issues a row activation command AC. Then, the SDRAM access control section 1 issues a read command RD in clock cycle 3. The SDRAM access control section 1 issues a deselect command DS in clock cycle 2, i.e., between the row activation command AC and the read command RD. It is assumed here that two clock cycles are required for RAS-CAS latency.
The SDRAM access control section 1 issues a bank deactivation command PR to deactivate the bank in clock cycle 6. It is assumed that five clock cycles are required from the issuance of the row activation command AC before the issuance of the bank deactivation command PR. Moreover, it is assumed that after the read command RD is issued in cycle 3, two clock cycles are required for CAS latency. Hence, the data signal 25 is output to the data bus in clock cycle 5.
The signal 21 is again asserted, i.e., in clock cycle 6, after the data (d0) of the SDRAM is output. The SDRAM requires two clock cycles from the issue of bank deactivation command PR until the issue of row activation command AC. Hence, the SDRAM row activation command AC is issued in clock cycle 8. A second SDRAM access (a1) is performed like the first SDRAM access (a0). The second SDRAM read data (d1) is output in clock cycle 12. In this example, twelve clock cycles are required from the first SDRAM access request until the output of the second SDRAM access data.
According to the conventional SDRAM control module, the cycle of the row activation AC and bank deactivation PR are repeated in the same row, each time the signal 21 is asserted. Therefore, the process is inefficient because many clock cycles are required when the same row in the same bank is continuously accessed many times.